```verilog
module multiplexer(
input [7:0] a,
input [7:0] b,
input [7:0] c,
input [7:0] d,
input [1:0] select,
output reg [7:0] data
);
always @(*) begin
case (select)
2'b00: data <= a;
2'b01: data <= b;
2'b10: data <= c;
2'b11: data <= d;
endcase
end
endmodule
```