Refer to [[T-FlipFlop|this T-FlipFlop implementation]].
```verilog
module tff_clock_divider
#(
parameter BIT_COUNT = 17
)
(
input clock,
input reset,
output divided_clock
);
wire [BIT_COUNT-1:0] tff_chain;
genvar i;
generate
for (i = 0; i < BIT_COUNT; i = i + 1) begin
if (i == 0) begin
t_flip_flop t_flip_flop(
.reset(reset),
.clock(clock),
.q(tff_chain[i])
);
end else begin
t_flip_flop t_flip_flop(
.reset(reset),
.clock(tff_chain[i-1]),
.q(tff_chain[i])
);
end
end
endgenerate
assign divided_clock = tff_chain[BIT_COUNT - 1];
endmodule
```