Refer to [[Counter|this counter implementation]]. The clock signal must be 1 kHz or higher to ensure that there's no flickering. You can use a clock divider [[Clock Divider Using T-FlipFlops|like this one]].
```verilog
module seven_segment_scanner(
input clock,
input reset,
output reg [3:0] anode
);
wire [1:0] selected_anode;
counter counter(
.clock(clock),
.reset(reset),
.number(selected_anode)
);
always @(posedge clock or posedge reset) begin
if (reset) begin
anode <= 4'b1111;
end else begin
case (selected_anode)
2'b00: anode <= 4'b1110;
2'b01: anode <= 4'b1101;
2'b10: anode <= 4'b1011;
2'b11: anode <= 4'b0111;
default: anode <= 4'b1111;
endcase
end
end
endmodule
```