**What is the difference between other programming languages and Verilog?**
The difference between other programming languages and Verilog is that *Verilog isn't sequentially executed.*
**What do Verilog source files describe?**
Verilog source files describe *the shape of a circuit.*
**What are three basic structures in Verilog?**
Three basic structures in Verilog include:
1. Modules.
2. Signals.
3. Expressions.
> **What do modules contain?**
> Modules contain *signals.*
>
> **What are signals driven by?**
> Signals are driven by *expressions.*
> > **What two forms can signals be?**
> > The two forms that signals can be are:
> > 1. `wire`.
> > 2. `reg`.
**What are the four basic bitwise operators for Verilog expressions?**
The four basic bitwise operators for Verilog expressions are:
1. `&` - bitwise AND.
2. `|` - bitwise OR.
3. `^` - bitwise XOR.
4. `~` - bitwise NOT.
**How do you create a project in Vivado?**
To create a project in Vivado:
1. Open Vivado.
2. Click *New Project.*
3. Name the project something meaningful.
4. Choose the project location.
5. Check *Create project subdirectory.*
6. Click *Next.*
7. Click *RTL Project.*
8. Uncheck *Do not specify sources at this time.*
9. Click *Next.*
10. Click *Add Files* and select the Vivado source files (ending with `.v`).
11. Click *Ok.*
12. Uncheck *Copy sources into project.*
13. If there's a `test.v` file, change the setting under *HDL Source For* to *Simulation only.*
14. Click *Next.*
15. Click *Add Files* and select the constraints file (usually named `constraints.xdc`).
16. Uncheck *Copy constraints files into project.*
17. Search for and select the appropriate part or board.
18. Click *Next.*
19. Verify that the New Project Summary matches what you selected previously.
20. Click *Finish.*
**What do you see in the Sources Pane of Vivado?**
In the Sources Pane of Vivado, you see *the source files in the project.*
> **What does it mean when a source file's name is in bold in the Sources Pane?**
> If a source file's name is in bold in the Sources Pane, it means *the file is a Top Level source for its given section.*
>
> **What are two things you should check in the Sources Pane if you're having issues programming or simulating?**
> If you're having issues programming or simulating, you should check in the Sources Pane if:
> 1. The correct source file is set as the Top Level source for a given section.
> 2. Make sure no simulation files show up under *Design Sources.*
>
> **How do you set a file as the Top Level source for a given section?**
> To set a file as the Top Level source for a given section, *right click the file and click "Set as top."*
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