1x4 Demultiplexer

module demultiplexer(
	input [7:0] data,
	input [1:0] select,
	output reg [7:0] a,
	output reg [7:0] b,
	output reg [7:0] c,
	output reg [7:0] d
);
	always @(*) begin
		a <= 8'b0;
		b <= 8'b0;
		c <= 8'b0;
		d <= 8'b0;

		case(select)
			2'b00: a <= data;
			2'b01: b <= data;
			2'b10: c <= data;
			2'b11: d <= data;
		endcase
	end
endmodule