Byte Memory

module byte_memory(
	input [7:0] data,
	input store,
	input clock,
	input reset,
	output reg [7:0] memory
);
	always @(posedge clock or posedge reset) begin
		if (reset) begin
			memory <= 8'b0;
		end else if (store) begin
			memory <= data;
		end
	end
endmodule