What Is Clock Latency And Clock Uncertainty by Vamsi Addagada

What are the two phases in the design of a clock signal?
The two phases in the design of a clock signal are:

  1. Ideal mode.
  2. Propagated mode.

When is the design of a clock signal in ideal mode?
The design of a clock signal is in ideal mode during RTL design, synthesis, and placement.

What does an ideal clock not have?
An ideal clock doesn't have a physical distribution tree.

When is the design of a clock signal in propagated mode?
The design of a clock signal is in propagated mode after Clock Tree Synthesis (CTS) inserts an actual tree of buffers into the design which carries the clock signal from the clock source pin to the the (thousands) of flipflops that need to get it.

When does Clock Tree Synthesis (CTS) happen?
CTS happens after placement and before routing.

What is clock latency?
Clock latency is a term in ideal mode that refers to the delay that is specified to exist between the source of the clock signal and the flip-flop pin.

How is clock latency defined?
Clock latency is defined by the user.

What is the clock delay referred to as when the clock is actually created?
When the clock is actually created, the clock delay is referred to as the Insertion Delay (ID).

What is the Insertion Delay (ID)?
The ID is a real, measurable delay path through a tree of buffers.

How is the clock delay sometimes interpreted?
The clock delay is sometimes interpreted as the desired target value for the insertion delay.

When can the clock signal arrive to all clock pins in ideal mode?
The clock signal can arrive to all clock pins in ideal mode simultaneously.

Is it possible for a the clock signal to always arrive at all clock pins simultaneously in real circuits?
No, it isn't possible for the clock signal to always arrive at all clock pins simultaneously in real circuits.

What is clock uncertainty?
Clock uncertainty is an ideal mode term for a span of time that is assumed to exist between clock signals arriving at different clock pins in the actual circuit.

What does it mean if a 1 ns clock has a 100 ps clock uncertainty?
If a 1 ns clock has a 100 ps clock uncertainty, that means the next clock tick will arrive in 1 ns plus or minus 50 ps.

What are two possible reasons why the clock doesn't always arrive exactly one clock period later?
Two possible reasons why the clock doesn't always arrive exactly one clock period later include:

  1. Clock skew.
  2. Clock jitter.

What is clock skew?
Clock skew is when one path through the clock tree can be longer than another path.

Can there still be clock skew even if the launching clock path and the capturing clock path are absolutely identical and why?
Yes, there can still be clock skew even if the launching clock path and the capturing clock are absolutely identical because of process variation and temperature variation across the chip's die.

What is clock jitter?
Clock jitter is when the clock period isn't constant and some periods are longer or shorter than others in a random fashion.