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1. 1's-complement-generator-made-from-xor-gates.png
2. 1-bit-full-adder.png
3. 1-bit-half-adder.png
4. 16-1-multiplexer-made-from-4-1-multiplexers.png
5. 2-1-multiplexer.png
6. 2-input-nand-gate-and-2-input-and-gate.png
7. 2-input-nor-gate-and-2-input-or-gate.png
8. 2-inverter-latch.png
9. 2x2-crossbar-switch.png
10. 2x4-decoder.png
11. 4-1-multiplexer-made-from-2-1-multiplexers.png
12. 4-1-multiplexer.png
13. 4-bit-adder.png
14. 4-bit-synchronous-counter-with-an-enable-and-clear-signal.png
15. and-gate-made-from-a-2-1-multiplexer.png
16. and2-gate.png
17. asynchronous-down-counting-frequency-divider-made-from-t-flipflops.png
18. asynchronous-up-counting-frequency-divider-made-from-t-flipflops.png
19. cascading-multiplexers.png
20. complementary-sr-latch.png
21. converting-a-logic-circuit-to-use-nand-gates-only.png
22. converting-a-logic-circuit-to-use-nor-gates-only.png
23. d-flipflop-made-from-a-t-flipflop-and-a-multiplexer.png
24. d-flipflop-made-from-a-t-flipflop-and-an-xor-gate.png
25. d-flipflop-made-from-a-t-flipflop.png
26. d-flipflop-made-from-two-d-latches.png
27. d-flipflop-with-a-preset-and-clear-signal.png
28. d-flipflop-with-an-asynchronous-and-synchronous-reset-signals.png
29. d-latch-made-from-only-nand-gates.png
30. d-latch.png
31. jk-flipflop-made-from-a-d-flipflop.png
32. jk-flipflop-made-from-a-t-flipflop.png
33. latch-with-a-set-and-reset-signal.png
34. multiplexer.png
35. or2-gate-made-from-a-2-1-multiplexer.png
36. or2-gate.png
37. parallel-register.png
38. programmable-array-logic.png
39. programmable-logic-array.png
40. serial-register.png
41. shannon's-version-of-the-full-adder.png
42. sr-latch-made-from-only-nand-gates.png
43. sr-latch-with-a-clock-signal.png
44. synchronous-counter-made-from-4-t-flipflops.png
45. synchronous-frequency-divider-made-from-t-flipflops.png
46. t-flipflop-made-from-a-multiplexer.png
47. t-flipflop-made-from-d-flipflop-and-an-xor-gate.png
48. t-flipflop.png
49. xor2-gate-made-from-a-2-1-multiplexer.png