tags:
- ece230
- bsu
- school
- digital-systems
- electronics
- lecture
- notes
- fall-2024
source: https://boisestatecanvas.instructure.com/courses/34549/files?preview=16896567
created: 2024-10-07
What are the two things machines remember?
The two things machines remember are:
What are the three characteristics of automatons?*
The three characteristics of automatons are that they:
...
What does it mean when the state of an automaton is stable?
When the state of an automaton is stable, it means that it will not change unless done by some external force.
What does it mean when the state of an automaton is well-defined?
When the state of an automaton is well-defined, it means that only a specific set of actions will be performed during the state.
What causes an automaton to switch from state to state?
An automaton switches from state to state because of an external force.
The states of an automaton are stable and well-defined.
A state is stable when it doesn't change unless by some external force. A state is well-defined when only a specific set of actions are performed during that state.
An automaton changes state by some external force.
What does the state of a multi-state machine affect?
The state of a multi-state machine affects the behavior.
What does the circuit of a multi-state machine already have inside?
The circuit of a multi-state machine already has the circuit blocks for executing ADD, SUB, MUL, MOD, etc.
What does the multi-state machine do with the circuit blocks?
The multi-state machine chooses which circuit blocks to activate depending on its state.
The slide mentions that a multi-state machine could potentially use a multiplexer to determine which circuit block is activated. That multiplexer's control signal is determined by the state number.
What does a latch do?
A latch remembers something for as long as it is asked to.
How does a latch operate?
A latch operates by looping mutual or complementary conditioning infinitely.
What is a latch?
A latch is a state holder, preserver, and sustainer.
What is the circuit diagram for a latch using two inverters?
The circuit diagram for a latch using using two inverters is:
What is the circuit diagram for a latch with a set and reset signal?
The circuit diagram for a latch with a set and reset signal is:
What is the truth table for the SR-Latch?
The truth table for the SR-Latch is:
Action | |||
---|---|---|---|
Hold | 0 | 0 | 0 or 1 |
Toggle 1 | 1 | 0 | 1 |
Toggle 2 | 0 | 1 | 0 |
DNC | 1 | 1 | 0 |
Do we care if
No, we don't care if
What is the hold state of an SR-Latch?
The hold state of an SR-Latch is when
What happens when
When
What happens when
When
What is the circuit diagram of a complementary SR-Latch?
The circuit diagram of a complementary SR-Latch is:
What signal enables the set and reset signals?
The signal that enables the set and reset signals is the clock signal.
How does a clock signal lock an SR-Latch?
A clock signal locks an SR-Latch by preventing theand inputs from passing through.
What is the circuit diagram for an SR-Latch with a clock signal?
The circuit diagram for an SR-Latch with a clock signal is:
...
What happens when the clock signal is 0?
When the clock signal is 0,
What happens when the clock signal is 1?
When the clock signal is 1,
What is the truth table for a complementary SR-Latch?
The truth table for a complementary SR-Latch is:
Clock | |||
---|---|---|---|
0 | 0 | 0 | Hold (Locked) |
0 | 0 | 1 | Hold (Locked) |
0 | 1 | 0 | Hold (Locked) |
0 | 1 | 1 | Hold (Locked) DNC |
1 | 0 | 0 | Hold |
1 | 0 | 1 | |
1 | 1 | 0 | |
1 | 1 | 1 | DNC |
...
What is it called when changes to a component's state are controlled by a clock signal?
When changes to a component's state are controlled by a clock signal, it is called being synchronized with the clock signal.
What are the characteristics of a synchronous circuit?
The characteristics of a synchronous circuit are:
What is a D-Latch?
A D-Latch is a latch with a single input
What is D-Latch short for?
D-Latch is short for Data Latch.
What is the circuit diagram for a D-Latch?
The circuit diagram for a D-Latch is:
What is the truth table for a D-Latch?
The truth table for a D-Latch is:
Clock | ||
---|---|---|
0 | ||
1 | 0 | 0 |
1 | 1 | 1 |
A D-Latch is an SR-Latch that requires less effort to use.
Is a D-Latch level-triggered or edge-triggered?
A D-Latch is level-triggered.
What does a D-Latch act like when there's an active clock signal?
When there's an active clock signal, a D-Latch acts like a buffer.
What does a D-Latch act like when there's an inactive clock signal?
When there's an inactive clock signal, a D-Latch acts like a memory cell.
What does a D-Latch hold and until when?
A D-Latch holds the state of the machine until the next active clock signal.
What do you need to do if you want the D-Latch to retain the state during the next active clock signal?
To retain the state during the next active clock signal, don't change the value of