Augustus De Morgan

What is the circuit diagram for an SR-Latch that only uses NAND gates?
The circuit diagram for an SR-Latch that only uses NAND gates is:
SR-Latch Made From Only NAND Gates.png

What is the circuit diagram of a D-Latch that only uses NAND gates?
The circuit diagram of a D-Latch that only uses NAND gates is:
D-Latch Made From Only NAND Gates.png

Edge Triggering

When does an edge-triggered circuit read input?
An edge-triggered circuit reads input only during the transition of the clock signal from active to inactive, or vice versa.

When does a positive edge-triggered circuit read input?
A positive edge-triggered circuit reads input during a 0 to 1 transition of the clock signal.

When does a negative edge-triggered circuit read input?
A negative edge-triggered circuit reads input during a 1 to 0 transition of the clock signal.

Is an edge-triggered circuit that stores information called a latch?
No, an edge-triggered circuit that stores information isn't called a latch.

Example of the difference between a level-triggered and a edge-triggered circuit

Difference Between Level-Triggered And Edge-Triggered Circuits.png

Flip-Flops: Clk Edge Triggered Signal Storage

How is a D-FlipFlop created?
A D-FlipFlop is created by cascading two D-Latches.

What is the circuit diagram for a negative edge-triggered D-FlipFlop created using two D-Latches?
The circuit diagram for a negative edge-triggered D-FlipFlop created using two D-Latches is:
D-FlipFlop Made From Two D-Latches.png

What is the first D-Latch which serves as the input for the D-FlipFlop called?
The first D-Latch, which serves as the input for the D-FlipFlop, is called the Leading Latch.

What is the second D-Latch which serves as the output for the D-FlipFlop called?
The second D-Latch, which serves as the output for the D-FlipFlop, is called the Following Latch.

When does a D-FlipFlop read input?
A D-FlipFlop reads input only at the leading latch during a rising or falling clock edge.

How long is the value of the D-FlipFlop held?
The value of the D-FlipFlop is held for the rest of the clock period.

How DFF works

What are the sequence of events in the process of a negative edge-triggered D-FlipFlop changing its state?
The sequence of events in the process of a negative edge-triggered D-FlipFlop changing its state are:

  1. The Leading Latch is in Read mode and the Following Latch is in Hold mode during the positive half of the clock signal.
  2. At the start of the negative clock signal, the Leading Latch goes into Hold mode and the Following Latch goes into Read mode.
  3. The Following Latch gets a copy of whatever was stored in the Leading Latch during the positive half of the clock.
  4. Since the Leading Latch is in Hold mode, new input can't leak through to the Following Latch. This preserves its state during the clock cycle.

How to make the DFF Positive Edge Triggered?

How do you make a D-FlipFlop positive edge-triggered?
To make a D-FlipFlop positive edge triggered, add an inverter before the clock signal reaches the Leading Latch and the inverter for the Following Latch.

What is the symbol for a negative edge-triggered D-FlipFlop?
The symbol for a negative edge-triggered D-FlipFlop is:
Negative Edge-Triggered D-FlipFlop.png

What is the symbol for a positive edge-triggered D-FlipFlop?
The symbol for a positive edge-triggered D-FlipFlop is:
Positive Edge-Triggered D-FlipFlop.png

Example of the differences between a D-Latch, a positive edge-triggered D-FlipFlop, and a negative edge-triggered D-FlipFlop

Comparison Of A D-Latch, A Negative Edge-Triggered D-FlipFlop, And A Positive Edge-Triggered D-FlipFlop.png