Introduction

What does it mean when a circuit changes its output when a certain signal is high?
When a circuit changes its output when a certain signal is high, it means the circuit is synchronous to that signal.

Clocks, Edges, and Flip-Flops Oh My!

What is a level sensitive circuit?
A level sensitive circuit is a circuit which changes as long as a certain signal is high.

What is an edge sensitive circuit?
An edge sensitive circuit is a circuit which changes when a certain signal switches from low to high.

Is a D-Latch level sensitive or edge sensitive?
A D-Latch is level sensitive.

What is the name for a D-Latch that's edge sensitive?
To name for a D-Latch that's edge sensitive is a D-FlipFlop.

What circuitry is need to make a D-FlipFlop from a D-Latch?
To make a D-FlipFlop from a D-Latch, the circuitry needed is a pulse detector that feeds into the enable or store input of the D-Latch.

How does a pulse detector work?
A pulse detector works by delaying and inverting the store signal so that the AND gate outputs 1 very briefly whenever the store signal goes high.

What keyword do you use in a sensitivity list to indicate that a block is sensitive to the rising edge of a signal in Verilog?
In Verilog, the keyword you use in a sensitivity list to indicate that a block is sensitive to the rising edge of a signal is the posedge keyword.

Example

A byte memory module which changes on the rising edge of a store signal in Verilog:

module byte_memory_ff(
	input [7:0] data,
	input store,
	output reg [7:0] memory
);

	always @(posedge store)
		memory <= data;

endmodule

What does FF stand for?
FF stands for FlipFlop.

What does DFF stand for?
DFF stands for D-FlipFlop.

What does the > symbol indicate on an input pin?
The > symbol on an input pin indicates that the input pin is edge triggered.

OK, So What is the Point?

What are all real computer memory systems based off of?
All real computer memory systems are based off of clocked circuits.

What is a clock?
A clock is any digital signal that toggles at a (usually) fixed frequency.

What is an example of something you can't do with level triggered logic?
An example of something you can't do with level triggered logic is counting.

What happens if you try making a circuit that adds 1 to itself using level triggered logic?
If you trying making a circuit that adds 1 to itself using level triggered logic, it will rapidly count as fast as the gates can toggle endlessly.

Example

A level sensitive counter in Verilog:

module level_counter(
	input count,
	input reset,
	output reg [7:0] value
);

	always @(count, reset) begin
		if (reset) begin
			value <= 'b0;
		end else if (count) begin
			value <= value + 1;
		end
	end

endmodule

Using FlipFlops as Clock Dividers

Example

An implementation of a D-FlipFlop in Verilog:

module dff(
    input reset,
    input clock,
    input D,
    output reg Q,
    output NotQ
);
    assign NotQ = ~Q;

    always @(posedge reset, posedge clock) begin
        if (reset) begin
            Q <= 0;
        end else if (clock) begin
            Q <= D;
        end
    end
endmodule

What happens when you feed a D-FlipFlop's NotQ output into its own D input?
When you feed a D-FlipFlop's NotQ output into its own D input, it divides the frequency of the clock signal by two and outputs it through Q.

What are components that divide the frequency of a clock signal called?
Components that divide the frequency of a clock signal are called clock dividers.

How can you achieve a particular clock signal frequency using D-FlipFlop clock dividers?
To achieve a particular clock signal frequency using D-FlipFlop clock dividers, you can chain them until you've divided the input clock speed by .

What is the frequency of the clock built into the Basys3 board?
The frequency of the clock built into the Basys3 board is 100 MHz.

How many chained D-FlipFlop clock dividers gives the best approximation for a 1 KHz signal if the input clock signal is 100 MHz, and what is that approximated signal?
The number of chained D-FlipFlop clock dividers that gives the best approximation for a 1 KHz signal, if the input clock signal is 100 MHz, is 17. That approximated signal is ~763 Hz.

Using Counters as Clock Dividers

What can you use if you need a more precise frequency than what D-FlipFlop clock dividers can do?
If you need a more precise frequency than what D-FlipFlop clock dividers can do, you can use counters as clock dividers.

How do you use a counter as a clock divider?
To use a counter as a clock divider:

  1. Find in the equation .
  2. Calculate to determine how many bits our counter needs in order to represent our target divisor.
  3. Set up a circuit at the output of a counter that triggers an output whenever the target frequency is reached and resets the counter back to 0.
Example

A clock divider that converts a 100 MHz clock frequency to a 1000 Hz clock frequency using a counter in Verilog:

module div(
    input clock,
    input reset,
    output reg div_clock
);
    reg intreset;
    wire [16:0] intcount;

    counter #(.WIDTH(17)) count(
        .clock(clock),
        .reset(intreset),
        .count(intcount)
    );

    // Want to create logic that
    // is synchronous to the rest
    // and count signals
    always @(reset, intcount) begin
        if (reset) begin
            // If we get reset, pass it through
            // to the counter
            // and reset out clock output
            intreset = 1;
            div_clock = 0;
        end else if (intcount == 100000) begin
            // Otherwise, if the count is equal
            // to our tickover point, then we
            // need to reset the counter and
            // toggle our output
            intreset = 1;
            div_clock = ~div_clock;
        end else begin
            // Otherwise, just let it count
            intreset = 0;
        end
        
    end

endmodule

What is the downside of using a counter as a clock divider?
The downside of using a counter as a clock divider is that it uses far more logic gates.

What should you use if your clock requirements are relatively loose?
If your clock requirements are relatively loose, you should use D-FlipFlop, or , clock dividers.

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