Continuous Assignment

What are two things continuous assignment can't do?
The two things continuous assignment can't do are:

  1. Wait for an event.
  2. Remember the past.

...

The SR-Latch

What is an SR-Latch used as?
An SR-Latch is used as a basic form of memory.

What does an SR-Latch use to remember its value?
To remember its value, an SR-Latch uses combinatorial loops.

What should you use to implement an SR-Latch in Verilog?
To implement an SR-Latch in Verilog, you should use behavioral Verilog.

What is the invalid state of an SR-Latch?
The invalid state of an SR-Latch is when the set and reset signals are set to 1.

Can the invalid state of an SR-Latch cause errors in certain implementations in Verilog?
Yes, the invalid state can cause errors in certain implementations in Verilog.

How can you avoid the invalid state of an SR-Latch?
To avoid the invalid state of an SR-Latch, you can use a D-Latch instead.

How does a D-Latch overcome the invalid state of the SR-Latch?
The D-Latch overcomes the invalid state of the SR-Latch by using a data and clock signal instead.

Truth Table and Considerations

Structural Implementation

What is the structural implementation for the SR-Latch in Verilog?
The structural implementation for the SR-Latch in Verilog is:

module structural_sr_latch(
	input Set,
	input Reset,
	output Q,
	output NotQ
);
	assign Q = ~(Reset | NotQ);
	assign NotQ = ~(Set | Q);
endmodule

Behavioral Implementation

What is the behavioral implementation for the SR-Latch in Verilog?
The behavioral implementation for the SR-Latch in Verilog is:

module behavioral_sr_latch(
	input Set,
	input Reset,
	output reg Q,
	output NotQ
);
	always @(Set, Reset) begin
		if (Set)
			Q <= 1;
		else if (Reset)
			Q <= 0;
	end

	assign NotQ = ~Q;
endmodule

Can you mix structural and behavioral Verilog?
Yes, you can mix structural and behavioral Verilog.

Making Higher Order Memory

How do you make higher order memory using D-Latches?
To make higher order memory using D-Latches:

  1. Use one D-Latch per bit of input.
  2. Wire the enable lines of every D-Latch to a single enable signal.
  3. Make the output of every D-Latch a single vector.

Making Computer Memory

How do you make computer memory using higher order memory?
To make computer memory out of higher order memory:

  1. Use a demultiplexer to select which block of higher order memory to write to.
  2. Use a demultiplexer to select which enable signal of a block of higher order memory is turned on.
  3. Use a multiplexer to select which block of higher order memory to output.

Array Syntax

What is a vector in Verilog?
In Verilog, a vector is a single signal which is a certain number of bits wide.

How do you create an 8-bit wire vector called vect?
To create an 8-bit wire vector called vect, you write:

wire [7:0] vect;

What is an array in Verilog?
In Verilog, an array is a certain number of different signals.

How do you create an array of 3 wires called arr?
To create an array of 3 wires called arr, you write:

wire arr[3:0];

How do you create an array of 3 8-bit wire vectors called arr_vec?
To create an array of 3 8-bit wire vectors called arr_vec, you write:

wire [7:0] arr_vec[3:0];

Array Syntax, Pt. 2

How do you grab one 1-bit signal from an array called arr?
To grab one 1-bit signal from an array called arr, you write:

arr[2];

How do you grab one 8-bit signal from an array of vectors called arr_vec?
To grab one 8-bit signal from an array of vectors called arr_vec, you write:

arr_vec[3];

How do you grab the 8th bit of an 8-bit signal from an array of vectors called arr_vec?
To grab the 8th bit of an 8-bit signal from an array of vectors called arr_vec, you write:

arr_vec[2][7];

Demultiplexer

How can you write a 1x4 4-bit demultiplexer in behavioral Verilog?
To write a 1x4 4-bit demultiplexer in behavioral Verilog, you write:

odule demultiplexer(
    input [3:0] data,
    input [1:0] sel,
    output reg [3:0] A,
    output reg [3:0] B,
    output reg [3:0] C,
    output reg [3:0] D
);
    always @(*) begin 
        case(sel)
            2'b00: {D, C, B, A} <= {4'b0, 4'b0, 4'b0, data}; 
            2'b01: {D, C, B, A} <= {4'b0, 4'b0, data, 4'b0};
            2'b10: {D, C, B, A} <= {4'b0, data, 4'b0, 4'b0};
            2'b11: {D, C, B, A} <= {data, 4'b0, 4'b0, 4'b0};
        endcase
    end
endmodule

Loop, genvar, and parameter

What is an example of using genvar and parameter to create instances of a module at run-time in Verilog?
An example of using genvar and parameter to create instances of a module at runtime in Verilog is:

module sample(
    input X, output Y
);
    assign Y = ~X;
endmodule

module genvar_example
#(
    parameter BIT_COUNT = 16 
)
(
    input [BIT_COUNT - 1:0] sw,
    output [BIT_COUNT - 1:0] led
);

    genvar i; 
    generate 
        for (i = 0; i < BIT_COUNT; i = i + 1) begin 
            sample inst( 
                .X(sw[i]), 
                .Y(led[i])
            );
        end
    endgenerate
endmodule

Instantiating Parameters

What is an example of using the genvar_example module and instantiating the BIT_COUNT parameter?
An example of using the genvar_example module and instantiating the BIT_COUNT parameter is:

module test();
    reg [15:0] sw;
    wire [15:0] led;

    genvar_example #(.BIT_COUNT(16)) uut( 
        .sw(sw),
        .led(led)
    );

    initial begin
        $dumpvars(0,test);
        sw = 0;
        #10;
        sw = 'hFFFF;
        #10;
    end
endmodule

Blocking vs. Non-blocking

What is the difference between blocking and non-blocking assignment?
The difference between blocking and non-blocking assignment is that blocking assignment occurs immediately and non-blocking assignment occurs at the end of the time step.

How do you use blocking assignment in Verilog?
To use blocking assignment in Verilog, you write:

A = B;

How do you use non-blocking assignment in Verilog?
To use non-blocking assignment in Verilog, you write:

A <= B;

What type of assignment operation should you always use unless you know what you're doing?
The type of assignment operation you should always use unless you know what you're doing is non-blocking assignment.